In general, a semiconductor memory device receives a power supply voltage VDD and a ground voltage VSS from an external device and generates internal voltages necessary for internal operations. Examples of the internal voltages include a core voltage VCORE supplied to a core region, a high voltage VPP used to drive a word line or used in an overdriving operation, and a back bias voltage VBB supplied as a bulk voltage of an NMOS transistor of the core region.
Examples of the internal voltages also include a cell plate voltage VCP used as a plate voltage of a cell capacitor, and a bit line precharge voltage VBLP used to precharge a bit line and the cell plate voltage VCP. In general, the cell plate voltage VCP is generated from the core voltage VCORE and is generated to be at half the level of the core voltage VCORE in order to minimize the power consumption.
In general, the cell plate voltage VCP and the bit line precharge voltage VBLP are generated by the same internal voltage generating circuit. When the level of the cell plate voltage VCP or the bit line precharge voltage VBLP is constant at half the level of the core voltage VCORE, a known internal voltage generating circuit stops driving the cell plate voltage VCP or the bit line precharge voltage VBLP. On the other hand, when the level of the cell plate voltage VCP or the bit line precharge voltage VBLP is higher or lower than half the level of the core voltage VCORE, the known internal voltage generating circuit drives the cell plate voltage VCP or the bit line precharge voltage VBLP. Here, the state of not driving the cell plate voltage VCP or the bit line precharge voltage VBLP, when the level of the cell plate voltage VCP or the bit line precharge voltage VBLP is constant at half the level of the core voltage VCORE, may be called a dead zone.
Meanwhile, the known internal voltage generating circuit is configured to compare the cell plate voltage VCP or the bit line precharge voltage VBLP with a plurality of reference voltages, and drive the cell plate voltage VCP or the bit line precharge voltage VBLP. When the cell plate voltage VCP or the bit line precharge voltage VBLP has a level between a high-level reference voltage and a low-level reference voltage, the known internal voltage generating circuit has the dead zone.
However, when the levels of reference voltages inputted into the internal voltage generating circuit varies according to a change in PVT (Process, Voltage and Temperature), that is, when an offset occurs, the level of a high-level reference voltage and the level of a low-level reference voltage may become reversed. When the levels of the reference voltages are reversed, the dead zone disappears and a short-circuit current occurs.